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CDCM6208V1FRGZR Datasheet(PDF) 38 Page  Texas Instruments 

CDCM6208V1FRGZR Datasheet(HTML) 38 Page  Texas Instruments 
38 / 87 page CDCM6208V1F SCAS943 – MAY 2015 www.ti.com When the output frequency plan calls for the use of some output dividers as fractional values, the following steps are needed to calculate the closest achievable frequencies for those using fractional output dividers and the frequency errors (difference between the desired frequency and the closest achievable frequency). • Based on system needs, decide the frequencies that need to have best possible jitter performance. • Once decided, these frequencies need to be placed on integer output dividers. • Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the common divisor algorithm. • Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider, input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the prescaler divider. • Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support the output frequencies that are not part of the common frequency plan from the common divisor algorithm already worked out. • For each fractional divider value, try to represent the fractional portion in a 20 bit binary scheme, where the first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is represented as 0.125 and so on. Continue this process until the entire 20 bit fractional binary word is exhausted. • Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the mathematical function of the frequency out of the prescaler divider divided by the achievable fractional divider. • The frequency error can then be calculated as the difference between the desired frequency and the closest achievable frequency. 10.5 Programming 10.5.1 Writing to the CDCM6208V1F To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208V1F. This bit signals if a read (first bit high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208V1F with each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in the register file. The 16 bits that follow are the data payload. If the host sends an incomplete message, (i.e. the host deasserts the SCS pin high prior to a complete message transmission), then the CDCM6208V1F aborts the transfer, and device makes no changes to the register file or the hardware. Figure 32 shows the format of a write transaction on the CDCM6208V1F SPI port. The host signals the CDCM6208V1F of the completed transfer and disables the SPI port by deasserting the SCS pin high. 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CDCM6208V1F 
